The protection of digital content and other information which may be required for operation of an electronic device, is often facilitated by encryption keys and passwords stored in various locations on an integrated circuit (IC). Access to the keys by someone other than the authorized user, or even access by the authorized user himself, could result in theft or misappropriation of copyrighted or otherwise protected digital material. Additionally, protected digital content or other secret information is often times decoded or unencrypted using the fore mentioned encryption keys, and stored temporarily by the IC within memory or register locations. Access to the memory or registers could also lead to the theft or misappropriation of content by unauthorized users.
New approaches to illicitly obtain protected digital content are coming into vogue wherein an unauthorized party may attempt to access protected digital materials at the IC level, by attempting access to IC internal registers and memory. These attacks utilize the IC design itself and attempt to take advantage of incorporated IC test features such as an operating mode know as “Design-for-Test” (DFT) mode. Design-for-Test attacks have thus created new concerns within the information security field and threaten the information security of various IC portions such as, but not limited to, static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), registers and flip-flops.
Recently proposed methods have attempted to address the protection of registers and latches from a DFT Attack. One such recently proposed method for protecting registers is to enumerate “secret-bearing” registers and exclude them from the DFT process. However this method has several disadvantages. First, by excluding registers it reduces the test coverage for DFT thus reducing the overall IC yield. Second, it is error-prone because it requires the designer to identify and manually remove the “secret-bearing” registers from the DFT process and the specific secret-bearing registers may be difficult or even impossible to accurately identify. Third, the method assumes that secret information is only contained in the registers but not in memory.
Another proposed method is based on obfuscation where the contents of different registers are multiplexed together in a pseudo-random fashion. This approach also has a disadvantage in that it requires a specialized DFT algorithm which is not supported by industry-standard Computer Aided Design (CAD) tools. A second disadvantage of this method is its reliance on obfuscation which may be subject to reverse-engineering by a determined hacker.
Therefore a need exists for methods and apparatuses to secure protected information from access by unauthorized users employing IC operating mode attacks such as Design-for-Test attacks or similar attacks taking advantage of an IC test mode.